This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In conventional memory applications, low power/energy systems typically use a low voltage of operation for memory. However, at low voltage of operation, conventional memory read margins may collapse, as worst (min) on-current (Ion) with variations may be equal or lower than worst (max) m-off-current (m*Ioff). Generally, on-current (Ion) refers to the current (I) on a bitline of a selected bitcell, and off-current (Ioff) refers to leakage current from unselected bitcells on the same bitline. For a memory array, where (m+1) bitcells share a bitline in a column, the worst case off-current is cm′ times Ioff, which may make read logic ‘0’ and read logic ‘1’ indistinguishable. Assuming bitcell size may be already optimized for (Ion/Ioff) for a given area, to achieve low Vmin of operation, ‘m’ needs to be significantly reduced, which may lead to shorter columns, and consequently smaller banks, and hence lower density of memory.